There is an increasing demand in semiconductor manufacturing to integrate high-voltage devices with high-performance (e.g., low voltage, high speed) devices for system on chip applications. Such integrated devices are useful in, for example, analog and mixed signal applications, especially in automotive areas.
However, in practice, integrating high-voltage and high-performance devices has proven problematic due in part to the differences in dimensional scaling of the respective devices. For example, high-performance devices operating at about 1 v to 1.8 v are generally implemented in the most recent (i.e., smallest) technology node, such as the current 45 nm and 32 nm nodes. A particular known implementation of high-performance devices is in thin-silicon SOI devices.
On the other hand, high-voltage devices operating in ranges between 1.8 v to over 50 v are typically implemented in older, larger technology nodes, such as the 180 nm node. The larger technology nodes provide better heat dissipation required by the higher operating voltages of the high-voltage devices. For example, high-voltage semiconductor devices are commonly manufactured using thick silicon body silicon-on-insulator (SOI) or bulk CMOS technologies. Particularly, high-voltage semiconductor devices may be fabricated using a planar field effect transistors (FET) with thick oxide, or with N or P channel drain-extended metal-oxide-semiconductor (DEMOS) transistor devices, such as lateral diffused MOS (LDMOS) devices.
When constrained by the gate oxide processes in use today, there are significant processing challenges to having gate oxides on the same die that support both 1.0 v devices and devices that operate at voltages that may exceed 20 v. This is due in part to the fact that a gate oxide layer on a particular die is typically optimized for either a high-performance device or a high-voltage device, but not for both at the same time.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.